We are looking for an experienced RTL Verification Engineer to verify complex IP/SoC designs using industry-standard methodologies. The engineer will be responsible for testbench architecture, stimulus generation, coverage closure, and ensuring complete functional correctness of RTL blocks.
Develop UVM-based or SystemVerilog testbenches for IP/SoC verification.
Understand design specifications and derive detailed verification plans.
Create and execute test scenarios, random tests, and directed testcases.
Develop scoreboards, checkers, monitors, and coverage models.
Achieve functional and code coverage closure.
Debug failures using waveforms, assertions, logs and work closely with design teams.
Perform regression management, root cause analysis, and testbench optimization.
Collaborate with designers, architects, and PD teams to ensure design quality and verification completeness.
Strong experience in SystemVerilog and UVM methodology.
Hands-on experience in verification of RTL blocks, subsystems, or SoCs.
Strong debugging skills using waveforms, assertions, and simulation logs.
Good understanding of digital design fundamentals (FSM, clocking, timing).
Experience with simulation tools (VCS, Questa, Xcelium).
Knowledge of coverage-driven verification (functional & code coverage).
Familiarity with AMBA protocols – AXI, AHB, APB.
Experience with SV Assertions (SVA) and checkers.
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