We are seeking a highly skilled RTL Hub Design Engineer to work on complex SoC/IP design development within a centralized RTL design team (“Hub”). The engineer will collaborate with cross-functional teams to deliver high-quality, scalable, and reusable RTL components across multiple projects.
Develop and maintain common RTL modules that serve as reusable components across SoC/IP programs.
Drive micro-architecture definition, specification development, and RTL implementation.
Deliver clean, optimized, and synthesis-friendly RTL in Verilog or SystemVerilog.
Perform lint, CDC, RDC, and synthesis constraint checks; debug and resolve issues.
Collaborate with architecture, verification, and physical design teams for design closure.
Participate in design reviews, documentation, and signoff activities.
Support integration teams with IP bring-up, debug, and timing closure.
Ensure adherence to coding guidelines, quality checks, and best practices across the hub.
Strong proficiency in Verilog/SystemVerilog RTL development.
Solid understanding of micro-architecture design, FSMs, clocking, resets, and timing.
Experience with standard AMBA protocols (AXI/AHB/APB) and interconnect fabrics.
Hands-on experience with:
Synthesis tools (DC, Genus)
Static checks (Lint, CDC/RDC)
Simulation tools (VCS, Questa, Xcelium)
Strong problem-solving and debugging skills at block and SoC level.
Ability to create clean design specs, timing diagrams, and architecture documents.
Experience collaborating in large, multi-site design teams.
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