Develop RTL-level digital designs for IP/SoC modules using Verilog/SystemVerilog.
Translate architecture specifications into micro-architecture and detailed RTL implementation.
Implement high-performance, low-power, and area-efficient digital circuits.
Ensure RTL is lint-clean, CDC-clean, and synthesis-friendly.
Work closely with Verification teams to resolve functional issues and improve coverage.
Collaborate with Physical Design teams for timing closure, constraint development, and ECOs.
Optimize designs to meet PPA (Power, Performance, Area) requirements.
Participate in design reviews and create relevant design documentation.
Strong knowledge of Verilog/SystemVerilog and digital design concepts.
Proficiency in building FSMs, datapaths, pipelines, FIFOs, clocking structures, etc.
Experience with RTL tools such as:
SpyGlass Lint / CDC
Design Compiler / Genus
VCS / Xcelium
Understanding of timing analysis, SDC constraints, and synthesis flow.
Knowledge of AMBA/AXI/AHB/APB or other digital interface protocols.
Strong debugging skills using waveform tools (DVE, Verdi, SimVision).
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