Design and develop Register Transfer Level (RTL) logic for digital blocks/sub-systems using Verilog/SystemVerilog.
Work on micro-architecture development, specification analysis, and design implementation.
Perform RTL coding, lint fixing, CDC clean-up, and synthesis-friendly design.
Collaborate with DV teams to support testbench integration and debug functional issues.
Work with physical design teams for timing closure, constraints development (SDC), and synthesis.
Optimize RTL for area, performance, power, and meet design constraints.
Participate in design reviews, documentation, and ensure high-quality deliverables.
Strong hands-on experience in Verilog/SystemVerilog RTL coding.
Good understanding of digital design fundamentals, FSMs, pipelining, clock/reset architectures.
Experience with Synopsys/Cadence tools—Design Compiler, SpyGlass, Lint, CDC, VCS, etc.
Knowledge of AMBA protocols (AXI/AHB/APB) or other standard digital interfaces.
Good debugging skills using simulation tools and waveform viewers.
Experience in timing analysis, synthesis flow, and constraints (SDC).
Understanding of DFT concepts like scan, MBIST (good to have).
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