We are seeking a strong RTL / Verilog Engineer with expertise in RTL development, coding, and implementation of digital IP blocks. The role involves translating micro-architecture specifications into high-quality, clean, synthesis-friendly Verilog RTL.
Develop RTL code in Verilog/SystemVerilog based on design specifications.
Understand micro-architecture and convert it into efficient RTL logic.
Implement FSMs, datapaths, pipelines, counters, FIFOs, and interface logic.
Perform lint, CDC, synthesis checks, and resolve violations.
Debug RTL issues using waveforms, assertions, and simulation results.
Work closely with verification teams to ensure functional correctness.
Participate in design reviews and contribute to specification documentation.
Optimize design for timing, area, and power.
Strong hands-on experience in Verilog RTL coding.
Good understanding of digital design fundamentals:
FSM design
Clock/reset domain logic
Timing concepts
Combinational & sequential logic
Experience with SystemVerilog for RTL (optional but valuable).
Familiarity with AMBA protocols (AXI/AHB/APB).
Experience with design tools:
Lint (SpyGlass/Questa Lint)
CDC/RDC tools
Simulation tools (VCS/Questa/Xcelium)
Synthesis tools (DC/Genus)
Strong RTL debugging skills.
Exposure to low-power design (UPF).
Knowledge of DFT concepts (scan, ATPG, MBIST).
Scripting experience in Python/Perl/Tcl.
Experience in SoC/IP integration.
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